AXI FFT Experiment with Generated Sine Data

Hello again, today, we are going to look at how to use AXI FFT ip core from Xilinx. Note that in this article, we are going to simulation the waveform only because we want to analyze the result from the AXI FFT. Moreover, this is the generated data only, next time we will use the data from ADC which we have been used with AXI SPI. The plan of attack will be show in the figure.

Firstly, we will generate sine wave using the code which is written by https://surf-vhdl.com/how-to-implement-sinusoidal-dds-vhdl/. The main concept there is used the numerically-controlled oscillator which will not address here. Secondly, absolutely, we will use AXI FFT for receive the data and it will send the data to AXI DMA to connect to the PS. Note that, in the simulation, we cannot simulate the PS phase due to it is the software. Last but not least, for simulation this hardware platform, we will use the AXI VIP which stand for AXI verification IP for simulation the PS-PL configuration. After, we have plan of attack here, we can build the block diagram in Vivado. The block diagram will be show here. Moreover, in the block diagram, we have DP_to_DMA block which is not address above but this block do only pack the data in terms of AXI-streaming protocol. It receive the raw data and create the MAXIS bus protocol to communicate with AXI FFT.

Now, we are going to look deeper in the AXI FFT ip core to see how we can config that.

Firstly, the first page show you how many channel and transform length you want to use. Here, we want to use just only one channel and just 1024 data length. If you understand FFT clearly, you can notice that this data length would effect how precise of this transform. For the architecture choice, we choose automatically select due to easy reason. However if you want an area optimized, you can choose Radix-2 or 4 something like that.

Then, we look at the implementation part which is about the data format and ordering. Now we choose Fixed point and for the ordering we choose natural order. The ordering here is important, if you choose others, the result from simulation could not be understand because you need to do ordering the data for analyze the frequency.

Finally, here is the implementation detailed which you can choose what component that you want to use. After that you can see the summary in the implementation detail in the left column of the core configuration which is shown below.

You can see that in the S_AXIS_CONFIG use only one bit to specify forward FFT or inverse FFT.

Now that, we finish the block diagram there. We are going to the simulation part which use Verilog test bench below.

Then, the result of the simulation is shown below. Firstly, we generated the sine wave and count the TVALID to 1024 for get the 1024 point of data. You can see in the M_AXIS_TVALID line where it is assert to 1 which mean it is valid. If you count correctly, there will be around 10 sine wave period in the 1024 point of data. Then, the waveform in magenta color is the result from AXI FFT which has the same length (1024 point of data). In this roughly view, we can see the latency of the AXI FFT which will effect the time when you want to use it in your design. Now we are look at the result of the FFT.

The result from AXI FFT has 32 bit which can separate into 2 kind of data. the first half is real number and the second half is complex number. Then, we need to zoom in to the data.

It can see that the spike is occur in the 10th position which is correspond to the 10 period of sine wave input.

In summary, this is only the simulation of the AXI FFT for show the result from that. It can be use as the reference when you want to design an accelerator DSP.

Thank you.